第8章 記憶體

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Bit.hdl

/**
 * 1-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 *                 else out does not change (out[t+1] = out[t])
 */

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    Mux(a=keep, b=in, sel=load, out=mux);
    DFF(in=mux, out=out, out=keep);

}

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Register.hdl

/**
 * 16-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 * else out does not change
 */

CHIP Register {
    IN in[16], load;
    OUT out[16];

    PARTS:
    Bit(in=in[0], load=load, out=out[0]);
    Bit(in=in[1], load=load, out=out[1]);
    Bit(in=in[2], load=load, out=out[2]);
    Bit(in=in[3], load=load, out=out[3]);
    Bit(in=in[4], load=load, out=out[4]);
    Bit(in=in[5], load=load, out=out[5]);
    Bit(in=in[6], load=load, out=out[6]);
    Bit(in=in[7], load=load, out=out[7]);
    Bit(in=in[8], load=load, out=out[8]);
    Bit(in=in[9], load=load, out=out[9]);
    Bit(in=in[10], load=load, out=out[10]);
    Bit(in=in[11], load=load, out=out[11]);
    Bit(in=in[12], load=load, out=out[12]);
    Bit(in=in[13], load=load, out=out[13]);
    Bit(in=in[14], load=load, out=out[14]);
    Bit(in=in[15], load=load, out=out[15]);
}

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM8.hdl

/**
 * Memory of 8 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address, a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);

    Register(in=in, load=loada, out=reg0);
    Register(in=in, load=loadb, out=reg1);
    Register(in=in, load=loadc, out=reg2);
    Register(in=in, load=loadd, out=reg3);
    Register(in=in, load=loade, out=reg4);
    Register(in=in, load=loadf, out=reg5);
    Register(in=in, load=loadg, out=reg6);
    Register(in=in, load=loadh, out=reg7);

    Mux8Way16(a=reg0, b=reg1, c=reg2, d=reg3, e=reg4, f=reg5, g=reg6, h=reg7, sel=address, out=out);
}

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl

/**
 * Memory of 64 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[3..5], a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);
    RAM8(in=in, load=loada, address=address[0..2], out=ram0);
    RAM8(in=in, load=loadb, address=address[0..2], out=ram1);
    RAM8(in=in, load=loadc, address=address[0..2], out=ram2);
    RAM8(in=in, load=loadd, address=address[0..2], out=ram3);
    RAM8(in=in, load=loade, address=address[0..2], out=ram4);
    RAM8(in=in, load=loadf, address=address[0..2], out=ram5);
    RAM8(in=in, load=loadg, address=address[0..2], out=ram6);
    RAM8(in=in, load=loadh, address=address[0..2], out=ram7);

    Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7, sel=address[3..5], out=out);
}

// This file is part of the materials accompanying the book
// "The Elements of Computing Systems" by Nisan and Schocken,
// MIT Press. Book site: www.idc.ac.il/tecs
// File name: projects/03/b/RAM512.hdl

/**
 * Memory of 512 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[6..8], a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);
    RAM64(in=in, load=loada, address=address[0..5], out=ram0);
    RAM64(in=in, load=loadb, address=address[0..5], out=ram1);
    RAM64(in=in, load=loadc, address=address[0..5], out=ram2);
    RAM64(in=in, load=loadd, address=address[0..5], out=ram3);
    RAM64(in=in, load=loade, address=address[0..5], out=ram4);
    RAM64(in=in, load=loadf, address=address[0..5], out=ram5);
    RAM64(in=in, load=loadg, address=address[0..5], out=ram6);
    RAM64(in=in, load=loadh, address=address[0..5], out=ram7);

    Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7, sel=address[6..8], out=out);
}

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[9..11], a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);
    RAM512(in=in, load=loada, address=address[0..8], out=ram0);
    RAM512(in=in, load=loadb, address=address[0..8], out=ram1);
    RAM512(in=in, load=loadc, address=address[0..8], out=ram2);
    RAM512(in=in, load=loadd, address=address[0..8], out=ram3);
    RAM512(in=in, load=loade, address=address[0..8], out=ram4);
    RAM512(in=in, load=loadf, address=address[0..8], out=ram5);
    RAM512(in=in, load=loadg, address=address[0..8], out=ram6);
    RAM512(in=in, load=loadh, address=address[0..8], out=ram7);
    Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7, sel=address[9..11], out=out);
}

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl

/**
 * Memory of 16K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then
 * the in value is loaded into the memory location specified by address
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM16K {
    IN in[16], load, address[15];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[12..14], a=loada, b=loadb, c=loadc, d=loadd, e=loade, f=loadf, g=loadg, h=loadh);
    RAM4K(in=in, load=loada, address=address[0..11], out=ram0);
    RAM4K(in=in, load=loadb, address=address[0..11], out=ram1);
    RAM4K(in=in, load=loadc, address=address[0..11], out=ram2);
    RAM4K(in=in, load=loadd, address=address[0..11], out=ram3);
    RAM4K(in=in, load=loade, address=address[0..11], out=ram4);
    RAM4K(in=in, load=loadf, address=address[0..11], out=ram5);
    RAM4K(in=in, load=loadg, address=address[0..11], out=ram6);
    RAM4K(in=in, load=loadh, address=address[0..11], out=ram7);

    Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7, sel=address[12..14], out=out);

}