第6章 暫存器
簡介¶
拴鎖器¶
正反器¶
RS 型正反器¶
D 型正反器¶
JK 型正反器¶
T 型正反器¶
暫存器¶
Verilog程式碼
Verilog測試檔案
移位暫存器¶
5位元左移暫存器¶
串列輸入四位元左移位串列輸出¶
Verilog程式碼
module siso_shift_register (clock, clear, in, out);
input clock, clear, in;
output out;
reg [3:0] register;
always @ (posedge clock) begin
if (clear) begin
register = 4'd0;
end else begin
register[3] = register[2];
register[2] = register[1];
register[1] = register[0];
register[0] = in;
end
end
assign out = register[3];
endmodule // siso_shift_register
Verilog測試檔案
`include "siso_shift_register.v"
module siso_shift_register_test ();
reg clock, clear, in;
wire out;
integer number;
siso_shift_register UUT (clock, clear, in, out);
initial begin
$display("| clock | clear | in | out |");
in = 1'b0;
clock = 1'b1;
clear = 1'b1;
#5;
clear = 1'b0;
#10;
for (number = 0; number < 5; number = number + 1) begin
in = 1;
#20;
end
#20;
clear = 1'b1;
#20;
clear = 1'b0;
for (number = 0; number < 8; number = number + 1) begin
in = number;
#20;
end
#20;
$finish;
end
always begin
#5;
$monitor("| %b | %b | %b | %b |", clock, clear, in, out);
#5;
clock = ~clock;
end
endmodule // siso_shift_register_test
測試結果
| clock | clear | in | out |
| 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 1 | 1 | 0 |
| 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 0 |
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 1 |
串列輸入四位元左移位並列輸出¶
Verilog程式碼
module sipo_shift_register (clock, clear, in, out);
input clock, clear, in;
output [3:0] out;
reg [3:0] register;
always @ (posedge clock) begin
if (clear) begin
register = 4'd0;
end else begin
register[3] = register[2];
register[2] = register[1];
register[1] = register[0];
register[0] = in;
end
end
assign out = register;
endmodule // sipo_shift_register
Verilog測試檔案
`include "sipo_shift_register.v"
module sipo_shift_register_test ();
reg clock, clear, in;
wire [3:0] out;
integer number;
sipo_shift_register UUT (clock, clear, in, out);
initial begin
in = 1'b0;
clock = 1'b1;
clear = 1'b1;
#5;
clear = 1'b0;
#10;
$display("| clock | clear | in | out |");
for (number = 0; number < 2; number = number + 1) begin
in = 1;
$monitor("| %b | %b | %b | %b |", clock, clear, in, out);
#20;
end
#20;
clear = 1'b1;
#20;
clear = 1'b0;
for (number = 0; number < 8; number = number + 1) begin
in = number;
$monitor("| %b | %b | %b | %b |", clock, clear, in, out);
#20;
end
$finish;
end
always begin
#10;
clock = ~clock;
end
endmodule // sipo_shift_register_test
測試結果
| clock | clear | in | out |
| 0 | 0 | 1 | 0000 |
| 1 | 0 | 1 | 0001 |
| 0 | 0 | 1 | 0001 |
| 0 | 0 | 1 | 0001 |
| 1 | 0 | 1 | 0011 |
| 0 | 0 | 1 | 0011 |
| 1 | 0 | 1 | 0111 |
| 0 | 0 | 1 | 0111 |
| 0 | 1 | 1 | 0111 |
| 1 | 1 | 1 | 0000 |
| 0 | 1 | 1 | 0000 |
| 0 | 0 | 0 | 0000 |
| 1 | 0 | 0 | 0000 |
| 0 | 0 | 0 | 0000 |
| 0 | 0 | 1 | 0000 |
| 1 | 0 | 1 | 0001 |
| 0 | 0 | 1 | 0001 |
| 0 | 0 | 0 | 0001 |
| 1 | 0 | 0 | 0010 |
| 0 | 0 | 0 | 0010 |
| 0 | 0 | 1 | 0010 |
| 1 | 0 | 1 | 0101 |
| 0 | 0 | 1 | 0101 |
| 0 | 0 | 0 | 0101 |
| 1 | 0 | 0 | 1010 |
| 0 | 0 | 0 | 1010 |
| 0 | 0 | 1 | 1010 |
| 1 | 0 | 1 | 0101 |
| 0 | 0 | 1 | 0101 |
| 0 | 0 | 0 | 0101 |
| 1 | 0 | 0 | 1010 |
| 0 | 0 | 0 | 1010 |
| 0 | 0 | 1 | 1010 |
| 1 | 0 | 1 | 0101 |
| 0 | 0 | 1 | 0101 |
累加器¶
用於做加法後自我存入到暫存器，在這裡拆開說明講解暫存器的使用範例。
Verilog程式碼
module accumulator (clock, clear, in, out);
input clock, clear;
input [3:0] in;
output [3:0] out;
reg [3:0] register;
always @ (posedge clock) begin
if (clear) begin
register = 4'd0;
end else begin
register += in;
end
end
assign out = register;
endmodule // accumulator
Verilog測試檔案
`include "accumulator.v"
module accumulator_test ();
reg clock, clear;
reg [3:0] in;
wire [3:0] out;
integer number;
accumulator UUT (clock, clear, in, out);
initial begin
in = 1'b0;
clock = 1'b1;
clear = 1'b1;
#5;
clear = 1'b0;
#10;
$display("| clock | clear | in | out |");
for (number = 0; number < 2; number = number + 1) begin
in = 1;
$monitor("| %b | %b | %b | %b |", clock, clear, in, out);
#20;
end
#20;
clear = 1'b1;
#20;
clear = 1'b0;
for (number = 0; number < 8; number = number + 2) begin
in = number;
$monitor("| %b | %b | %b | %b |", clock, clear, in, out);
#20;
end
$finish;
end
always begin
#10;
clock = ~clock;
end
endmodule // accumulator_test
測試結果
| clock | clear | in | out |
| 0 | 0 | 0001 | 0000 |
| 1 | 0 | 0001 | 0001 |
| 0 | 0 | 0001 | 0001 |
| 0 | 0 | 0001 | 0001 |
| 1 | 0 | 0001 | 0010 |
| 0 | 0 | 0001 | 0010 |
| 1 | 0 | 0001 | 0011 |
| 0 | 0 | 0001 | 0011 |
| 0 | 1 | 0001 | 0011 |
| 1 | 1 | 0001 | 0000 |
| 0 | 1 | 0001 | 0000 |
| 0 | 0 | 0000 | 0000 |
| 1 | 0 | 0000 | 0000 |
| 0 | 0 | 0000 | 0000 |
| 0 | 0 | 0010 | 0000 |
| 1 | 0 | 0010 | 0010 |
| 0 | 0 | 0010 | 0010 |
| 0 | 0 | 0100 | 0010 |
| 1 | 0 | 0100 | 0110 |
| 0 | 0 | 0100 | 0110 |
| 0 | 0 | 0110 | 0110 |
| 1 | 0 | 0110 | 1100 |
| 0 | 0 | 0110 | 1100 |
電路名稱¶
Verilog程式碼
Verilog測試檔案
測試結果