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第3章 邏輯閘層次簡化

簡介

邏輯化簡

卡諾圖

列表法

NAND

  • IC設計中的基本邏輯閘
  • 容易製作
  • 表現傑出
  • 發展許久，可以實踐許多邏輯閘–>也稱為「萬用閘」(Universal Gate)
module nand_and (a, b, out);
  input a, b;
  output out;

  assign out = ~(a & b);

endmodule // nand_and

通常會通過「反相器」(NOT)的組合方式達到，以下是最小單元AND跟OR使用NAND與NOT實現。

轉換方式

  1. 最簡[[/docs/knowledge-network-database-repository/布林函數]]，使用[[/docs/knowledge-network-database-repository/積項和]]
  2. 轉換成NAND，AND用NAND，OR用OR-NOT

轉換範例

NOT

2021-09-22 22-33-40 的螢幕擷圖

Verilog程式碼 
module nand_and (in, out);
  input in;
  output out;

  assign out = ~(in & in);

endmodule // nand_and
HDL 程式碼 
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Not.hdl

/**
 * Not gate:
 * out = not in
 */

CHIP Not {
    IN in;
    OUT out;

    PARTS:
    // Put your code here:
    Nand(a=in, b=in, out=out);
}
in out
0 1
1 0

AND

2021-09-22 22-48-06 的螢幕擷圖

Verilog程式碼 
module nand_and (a, b, out);
  input a, b;
  output out;

  assign out = a ~& b;

endmodule // nand_and
HDL 程式碼 
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/And.hdl

/**
 * And gate:
 * out = 1 if (a == 1 and b == 1)
 *       0 otherwise
 */

CHIP And {
    IN a, b;
    OUT out;

    PARTS:
        Nand(a=a, b=b, out=ab);
        Not(in=ab, out=out);
}
a b out
0 0 0
0 1 0
1 0 0
1 1 1

OR

2021-09-22 23-15-20 的螢幕擷圖

Verilog程式碼 
module nand_and (a, b, out);
  input a, b;
  output out;

  assign out = ~(~a & ~b);

endmodule // nand_and
Verilog測試檔案
HDL 程式碼 
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Or.hdl

 /**
 * Or gate:
 * out = 1 if (a == 1 or b == 1)
 *       0 otherwise
 */

CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    Not(in=a, out=abar);
    Not(in=b, out=bbar);
    Nand(a=abar, b=bbar, out=out);
}
a b out
0 0 0
0 1 1
1 0 1
1 1 1

XOR

2021-09-22 23-46-15 的螢幕擷圖

Verilog程式碼 
module nand_and (a, b, out);
  input a, b;
  output out;
  wire nand1_out, nand2_out, nand3_out;

  assign nand1_out = ~(a & b);
  assign nand2_out = ~(nand1_out & a);
  assign nand3_out = ~(nand1_out & b);
  assign out = ~(nand2_out & nand3_out);

endmodule // nand_and
Verilog測試檔案
HDL 程式碼 
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Xor.hdl

/**
 * Exclusive-or gate:
 * out = not (a == b)
 */

CHIP Xor {
    IN a, b;
    OUT out;

    PARTS:
      Nand(a=a , b=b, out=nand1out);
      Nand(a=a, b=nand1out, out=nand2out);
      Nand(a=nand1out, b=b, out=nand3out);
      Nand(a=nand2out, b=nand3out, out=out);
}
a b out
0 0 0
0 1 1
1 0 1
1 1 0